1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of improving junction leakage in a cobalt salicide process in the fabrication of integrated circuits.
2. Description of the Prior Art
In the fabrication of integrated circuit devices, silicidation processes are often used in order to obtain higher circuit performance. In silicidation, a refractory metal layer is deposited and then annealed. The underlying silicon reacts with the refractory metal layer to produce a silicide overlying the gate electrode and source and drain regions. The silicided gate and source/drain regions have lower resistance than non-silicided regions, especially in smaller geometries, and hence, higher circuit performance. Cobalt has been used in the art to form silicided device structures. Typically, a titanium nitride capping layer is deposited over the cobalt layer before silicidation to protect the CoSix layer from oxygen contamination during RTA. Oxygen contamination causes poor resistance and poor silicide formation. So, the TiN capping layer can improve CoSixformation quality. However, a major issue is poor CoSix thickness uniformity. So, some devices may suffer high junction leakage. It has been reported that a capping titanium layer instead of a titanium nitride layer can improve junction leakage. However, it is hard to control titanium because it has a narrow process margin.
U.S. Pat. No. 5,970,370 to Besser et al teaches forming a titanium nitride capping layer over a cobalt layer, then evacuating the N2 gas from the sputtering chamber and depositing a titanium layer over the titanium nitride layer. This mechanism is directed to chamber containment and oxide outgassing reduction, not for cobalt silicide uniformity improvement. U.S. Pat. No. 5,736,461 to Berti et al discloses a titanium nitride or titanium tungsten capping layer over cobalt. U.S. Pat. No. 6,121,139 to Chang et al teaches a titanium silicide process. A titanium layer is deposited. N2 gas is added at 2 to 20% to form a titanium-rich titanium nitride layer over the titanium layer. A second pure titanium layer is deposited. An annealing forms titanium silicide. The capping layer in this patent is a very complicated sandwich layer. The process stability is hard to control. The titanium-rich titanium nitride layer""s purpose is to resist silicon diffusion into the titanium to prevent bridging. This issue does not exist in the cobalt silicide process. U.S. Pat. Nos. 6,136,705 and 6,103,610, both to Blair show a titanium layer over cobalt and a titanium nitride layer over the titanium layer. The double capping layer of these patents is formed by two different processes using different process conditions and tool arrangements. Thickness uniformity can be improved by Blair""s process, but resistance is still too high.
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method for improving junction leakage performance in a cobalt salicide process in the fabrication of integrated circuits.
It is a further object of the invention to provide an improved cobalt silicide process having reduced junction leakage in the fabrication of integrated circuits.
Yet another object is to provide an improved cobalt silicide process having a titanium-rich titanium nitride/titanium nitride capping layer to improve junction leakage.
In accordance with the objects of the invention, a cobalt silicide process having a titanium-rich titanium nitride/titanium nitride capping layer to improve junction leakage is achieved. Semiconductor device structures to be silicided are formed in and on a semiconductor substrate. A cobalt layer is deposited overlying the semiconductor device structures. A titanium-rich titanium nitride/titanium nitride capping layer is deposited overlying the cobalt layer. Thereafter, a cobalt silicide layer is formed on the semiconductor device structures. The titanium-rich titanium nitride/titanium nitride capping layer and an unreacted portion of the cobalt layer are removed to complete fabrication of the integrated circuit device.